Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 522 of 982
REJ09B0054-0600
14.3.21 IEBus Receive Status Register (IERSR)
IERSR detects receive data ready, receive start, transmit/receive normal completion, or receive
completion with an error. Each status flag in IERSR corresponds to a bit in the IEIER that
enables/disables each interrupt.
Bit Bit Name
Initial
Value
R/W Description
7 RxRDY 1 R/W Receive Data Ready
Indicates that the receive data is stored in IERBR and that
the receive data can be read. This flag is automatically
cleared by DTC
*
data transfer. When data is transmitted by
the CPU, this flag must be cleared by software.
[Setting condition]
When data reception has been completed normally and
receive data has been loaded to IERBR.
[Clearing conditions]
• When writing 0 after reading RxRDY = 1
• When IERBR data is read by the DTC by a RxRDY
request.
Note: This flag cannot be cleared on the end byte of the
DTC transfer.
6 to 3 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be modified.
2 RxS 0 R/W Receive Start Detection
Indicates that the IEB starts reception.
[Setting conditions]
• Master reception: When the message length field has
been received from the slave unit correctly after the
arbitration is won and the control field transmission is
completed
• Slave reception: When the message length field has
been received from the master unit correctly
[Clearing condition]
When writing 0 after reading RxS = 1