Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 511 of 982
REJ09B0054-0600
14.3.15 IEBus Lock Address Register 1 (IELA1)
IELA1 specifies the lower 8 bits of a locked address when a unit is locked. Data in this register is
valid when the LCK flag in IEFLG is set to 1. This register cannot be modified.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
ILA7
ILA6
ILA5
ILA4
ILA3
ILA2
ILA1
ILA0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Lower 8 Bits of IEBus Lock Address
Store the lower 8 bits of the master unit address
when a unit is locked.
14.3.16 IEBus Lock Address Register 2 (IELA2)
IELA2 is an 8-bit read-only register that specifies the upper 4 bits of a locked address when a unit
is locked. Data in this register is valid when the LCK flag in IEFLG is set to 1. This register
cannot be modified.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ All 0 R Reserved
These bits are always read as 0.
3
2
1
0
ILA11
ILA10
ILA9
ILA8
0
0
0
0
R
R
R
R
Upper 4 Bits of IEBus Locked Address
Store the upper 4 bits of the master unit address
when a unit is locked.