Datasheet

Rev. 6.00 Mar. 18, 2010 Page lv of lx
REJ09B0054-0600
Table 11.29 Cascaded Combinations .........................................................................................409
Table 11.30 PWM Output Registers and Output Pins................................................................412
Table 11.31 Clock Input Pins in Phase Counting Mode.............................................................416
Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 .......................................418
Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2 .......................................419
Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3 .......................................420
Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4 .......................................421
Table 11.36 TPU Interrupts........................................................................................................424
Section 12 8-Bit Timers
Table 12.1
Pin Configuration...................................................................................................443
Table 12.2 8-Bit Timer Interrupt Sources ................................................................................458
Table 12.3 Timer Output Priorities ..........................................................................................461
Table 12.4 Switching of Internal Clock and TCNT Operation.................................................462
Section 13 Watchdog Timer (WDT)
Table 13.1
Pin Configuration...................................................................................................467
Table 13.2 WDT Interrupt Source............................................................................................476
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Table 14.1
Mode Types............................................................................................................483
Table 14.2 Transfer speed and Maximum Number of Transfer Bytes in Each
Communications Mode ..........................................................................................484
Table 14.3 Contents of Message Length Bits...........................................................................489
Table 14.4 Control Bit Contents...............................................................................................493
Table 14.5 Control Field for Locked Slave Unit......................................................................494
Table 14.6 Pin Configuration...................................................................................................497
Section 15 Serial Communication Interface (SCI)
Table 15.1
Pin Configuration...................................................................................................551
Table 15.2 The Relationships between the N Setting in BRR and Bit Rate B .........................571
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) ..................................572
Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................576
Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)..................577
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ......................578
Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)......579
Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372) ......................................................................................580
Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(When S = 372) ......................................................................................................580