Datasheet

Rev. 6.00 Mar. 18, 2010 Page liii of lx
REJ09B0054-0600
Section 5 Interrupt Controller
Table 5.1
Pin Configuration...................................................................................................129
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................137
Table 5.3 Interrupt Control Modes.........................................................................................142
Table 5.4 Interrupts Selected in Each Interrupt Control Mode (1).........................................143
Table 5.5 Interrupts Selected in Each Interrupt Control Mode (2).........................................144
Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode ...........144
Table 5.7 Interrupt Response Times.......................................................................................150
Table 5.8 Number of States in Interrupt Handling Routine Execution Status........................151
Table 5.9 Interrupt Source Selection and Clear Control.........................................................153
Section 7 Bus Controller
Table 7.1
Pin Configuration...................................................................................................167
Table 7.2 Bus Specifications for Each Area (Basic Bus Interface)........................................177
Table 7.3 Data Buses Used and Valid Strobes.......................................................................182
Table 7.4 Pin States in Idle Cycle ..........................................................................................196
Table 7.5 Pin States in Bus Released State ............................................................................197
Section 8 DMA Controller (DMAC)
Table 8.1
Pin Configuration...................................................................................................205
Table 8.2 Short Address Mode and Full Address Mode (Channel 0).....................................206
Table 8.3 DMAC Activation Sources.....................................................................................232
Table 8.4 DMAC Transfer Modes..........................................................................................234
Table 8.5 Register Functions in Sequential Mode..................................................................236
Table 8.6 Register Functions in Idle Mode ............................................................................239
Table 8.7 Register Functions in Repeat Mode........................................................................241
Table 8.8 Register Functions in Single Address Mode ..........................................................245
Table 8.9 Register Functions in Normal Mode ......................................................................248
Table 8.10 Register Functions in Block Transfer Mode...........................................................251
Table 8.11 DMAC Channel Priority Order ..............................................................................271
Table 8.12 Interrupt Sources and Priority Order ......................................................................275
Section 9 Data Transfer Controller (DTC)
Table 9.1
Activation Source and DTCER Clearance .............................................................288
Table 9.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................291
Table 9.3 Register Information in Normal Mode...................................................................294
Table 9.4 Register Information in Repeat Mode....................................................................295
Table 9.5 Register Information in Block Transfer Mode .......................................................296
Table 9.6 DTC Execution Status............................................................................................300