Datasheet

Section 13 Watchdog Timer (WDT)
Rev. 6.00 Mar. 18, 2010 Page 478 of 982
REJ09B0054-0600
When writing 0 to the WOVF bit
When writing to the RSTE and RSTS bits
Address:
Address:
15 8 7 0
H'A5
H'FF76
H'00
15 8 7 0
H'5A
H'FF76
Write data
Figure 13.7 Writing to RSTCSR
(3) Reading from TCNT, TCSR, and RSTCSR
These registers can be read in the same way normal registers are read. TCSR is allocated at
address H'FF74, TCNT at address H'FF75, and RSTCSR at address H'FF77.
13.6.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 13.8 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle
Counter write data
Figure 13.8 Contention between TCNT Write and Increment