Datasheet

Section 13 Watchdog Timer (WDT)
Rev. 6.00 Mar. 18, 2010 Page 476 of 982
REJ09B0054-0600
13.4.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF)
With WDT_0 the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode.
If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal is generated for the
entire chip. (The WOVI interrupt is not generated.) This timing is illustrated in figure 13.5.
φ
TCNT
H'FF H'00
Overflow signal
(internal signal)
WOVF
Internal reset
signal
518 states (WDT_0)
515/516 states (WDT_1)
Figure 13.5 Timing of WOVF Setting
13.5 Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
If an NMI interrupt request has been chosen in the watchdog timer mode, an NMI interrupt request
is generated when a TCNT overflow occurs.
Table 13.2 WDT Interrupt Source
Name Interrupt Source Interrupt Flag
WOVI TCNT overflow (interval timer mode) OVF
NMI TCNT overflow (watchdog timer mode) OVF