Datasheet

Section 13 Watchdog Timer (WDT)
Rev. 6.00 Mar. 18, 2010 Page 470 of 982
REJ09B0054-0600
• TCSR_1
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)
*
1
Overflow Flag
Indicates that TCNT has overflowed. Only a 0 can
be written to this bit, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF to
H'00)
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR*
2
when OVF = 1, then
writing 0 to OVF
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode (an interval timer interrupt
(WOVI) is requested to CPU)
1: Watchdog timer mode (a power-on reset or NMI
interrupt is requested to CPU)
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
4 PSS 0 R/W Prescaler Select
Selects the clock source input to TCNT of WDT_1
0: TCNT counts divided clock of φ-base prescaler
(PSM)
1: TCNT counts divided clock of φ
SUB
-base
prescaler (PSS)
3 RST/NMI 0 R/W Reset or NMI (RST/NMI)
When TCNT overflows in watchdog timer mode,
either a power-on reset or NMI interrupt is
selected.
0: An NMI interrupt is requested
1: Reset is requested