Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 460 of 982
REJ09B0054-0600
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 12.11 Contention between TCNT Write and Increment
12.8.3 Contention between TCOR Write and Compare-Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.12 shows this operation.
φ
Address TCOR address
Internal write signal
TCNT
TCOR
NM
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare-match signal
Prohibited
Figure 12.12 Contention between TCOR Write and Compare-Match