Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 459 of 982
REJ09B0054-0600
12.8 Usage Notes
12.8.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows
this operation.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12.10 Contention between TCNT Write and Clear
12.8.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 12.11 shows this operation.