Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 455 of 982
REJ09B0054-0600
12.5.3 Timing of Timer Output when a Compare-Match Occurs
When a compare-match occurs, the timer output changes as specified by the output select bits
(OS3 to OS0) in TCSR. Figure 12.6 shows the timing when the output is set to toggle at compare-
match A.
φ
Compare-match A
signal
Timer output
pin
Figure 12.6 Timing of Timer Output
12.5.4 Timing of Compare-Match Clear when a Compare-Match Occurs
TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 12.7 shows the timing of this operation.
φ
N H'00
Compare-match
signal
TCNT
Figure 12.7 Timing of Compare-Match Clear