Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 447 of 982
REJ09B0054-0600
12.3.5 Timer Control/Status Register (TCSR)
TCSR indicates status flags and controls compare-match output.
• TCSR_0
Bit Bit Name
Initial
Value
R/W Description
7 CMFB 0 R/(W)
*
Compare-Match Flag B
[Setting condition]
When TCNT = TCORB
[Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in
CMFB
• When DTC is activated by CMIB interrupt while
DISEL bit of MRB in DTC is 0 with the transfer
counter not being 0
6 CMFA 0 R/(W)
*
Compare-Match Flag A
[Setting condition]
When TCNT = TCORA
[Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in
CMFA
• When DTC is activated by CMIA interrupt while
DISEL bit of MRB in DTC is 0 with the transfer
counter not being 0
5 OVF 0 R/(W)
*
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ADTE 0 R/W A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A
are disabled
1: A/D converter start requests by compare-match A
are enabled