Datasheet

Rev. 6.00 Mar. 18, 2010 Page xlviii of lx

REJ09B0054-0600

Figure 15.44 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)........................................................631

Section 16 I

C Bus Interface (IIC) (Option)

Figure 16.1 Block Diagram of I

C Bus Interface.....................................................................635

Figure 16.2 I

C Bus Interface Connections (Example: This LSI as Master) ...........................636

Figure 16.3 I

C Bus Data Formats (I

C Bus Formats).............................................................654

Figure 16.4 I

C Bus Data Format (Serial Format)...................................................................654

Figure 16.5 I

C Bus Timing.....................................................................................................654

Figure 16.6 Flowchart for IIC Initialization (Example) ..........................................................655

Figure 16.7 Flowchart for Master Transmit Mode (Example) ................................................656

Figure 16.8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) .......658

Figure 16.9 Example of Master Transmit Mode Stop Condition Generation Timing

(MLS = WAIT = 0)..............................................................................................658

Figure 16.10 Flowchart for Master Receive Mode (Receiving Multiple Bytes)

(WAIT = 1) (Example).........................................................................................660

Figure 16.11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)

(Example).............................................................................................................661

Figure 16.12 Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1)...........................................................................663

Figure 16.13 Example of Master Receive Mode Stop Condition Generation Timing

(MLS = ACKB = 0, WAIT = 1)...........................................................................664

Figure 16.14 Flowchart for Slave Transmit Mode (Example)...................................................665

Figure 16.15 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0).....667

Figure 16.16 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0).....668

Figure 16.17 Sample Flowchart for Slave Transmit Mode .......................................................669

Figure 16.18 Example of Slave Transmit Mode Operation Timing (MLS = 0)........................671

Figure 16.19 IRIC Setting Timing and SCL Control ................................................................672

Figure 16.20 Block Diagram of Noise Canceler .......................................................................674

Figure 16.21 Points for Attention Concerning Reading of Master Receive Data......................680

Figure 16.22 Flowchart and Timing of Start Condition Instruction Issuance for

Retransmission.....................................................................................................681

Figure 16.23 Timing of Stop Condition Issuance......................................................................682

Figure 16.24 IRIC Flag Clearance in WAIT = 1 Status ............................................................682

Figure 16.25 ICDR Read and ICCR Access Timing in Slave Transmit Mode .........................683

Figure 16.26 TRS Bit Setting Timing in Slave Mode ...............................................................684

Figure 16.27 Diagram of Erroneous Operation Wen Arbitration Is Lost..................................686

Figure 16.28 IRIC Flag Clearing Timing in Wait Operation.....................................................687