Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 437 of 982
REJ09B0054-0600
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
N M
Buffer register write data
Figure 11.49 Contention between Buffer Register Write and Compare Match
11.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T
1
state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 11.50 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 11.50 Contention between TGR Read and Input Capture