Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 397 of 982
REJ09B0054-0600
11.3.9 Timer Synchronous Register (TSYR)
In the H8S/2227 Group, TSYR selects independent or synchronous TCNT operation for channels
0 to 2. In other groups, TSYR selects independent or synchronous TCNT operation for channels 0
to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit Bit Name Initial value R/W Description
7, 6 — All 0 R/W Reserved
The write value should always be 0.
5
4
3
2
1
0
SYNC5
*
SYNC4
*
SYNC3
*
SYNC2
SYNC1
SYNC0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Timer Synchronization 5 to 0
These bits select whether operation is independent of
or synchronized with other channels.
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)
Note: * In the H8S/2227 Group, bits 5 to 3 are reserved. The write value should always be 0.