Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 391 of 982
REJ09B0054-0600
11.3.4 Timer Interrupt Enable Register (TIER)
The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU
of the H8S/2227 Group has a total of three TIER registers, one each for channels 0 to 2. In other
groups, the TPU has a total of six TIER registers, one each for channels 0 to 5.
Bit Bit Name Initial value R/W Description
7 TTGE 0 R/W A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6 — 1 — Reserved
This bit is always read as 1 and cannot be
modified.
5 TCIEU 0 R/W Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by
the TCFU flag when the TCFU flag in TSR is set to
1 in channels 1, 2, 4
*
, and 5
*
.
In channels 0 and 3
*
, bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4 TCIEV 0 R/W Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by
the TCFV flag when the TCFV flag in TSR is set to
1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3 TGIED 0 R/W TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by
the TGFD bit when the TGFD bit in TSR is set to 1
in channels 0 and 3
*
.
In channels 1, 2, 4
*
, and 5
*
, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled