Datasheet

Rev. 6.00 Mar. 18, 2010 Page xlii of lx
REJ09B0054-0600
Figure 7.2 Overview of Area Divisions.................................................................................175
Figure 7.3 CSn Signal Output Timing (n = 0 to 7)................................................................178
Figure 7.4 On-5Chip Memory Access Cycle ........................................................................179
Figure 7.5 Pin States during On-Chip Memory Access.........................................................179
Figure 7.6 On-Chip Peripheral Module Access Cycle ..........................................................180
Figure 7.7 Pin States during On-Chip Peripheral Module Access.........................................180
Figure 7.8 Access Sizes and Data Alignment Control (8-Bit Access Space)........................181
Figure 7.9 Access Sizes and Data Alignment Control (16-Bit Access Space)......................182
Figure 7.10 Bus Timing for 8-Bit 2-State Access Space.........................................................183
Figure 7.11 Bus Timing for 8-Bit 3-State Access Space.........................................................184
Figure 7.12 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)...185
Figure 7.13 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)....186
Figure 7.14 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) ........................187
Figure 7.15 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)...188
Figure 7.16 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)....189
Figure 7.17 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) ........................190
Figure 7.18 Example of Wait State Insertion Timing..............................................................191
Figure 7.19 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) ..............193
Figure 7.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) ..............193
Figure 7.21 Example of Idle Cycle Operation (1)...................................................................194
Figure 7.22 Example of Idle Cycle Operation (2)...................................................................195
Figure 7.23 Relationship between Chip Select (CS) and Read (RD) ......................................196
Figure 7.24 Bus-Released State Transition Timing.................................................................198
Section 8 DMA Controller (DMAC)
Figure 8.1 Block Diagram of DMAC....................................................................................204
Figure 8.2 Areas for Register Re-Setting by DTC (Channel 0A)..........................................230
Figure 8.3 Operation in Sequential Mode..............................................................................237
Figure 8.4 Example of Sequential Mode Setting Procedure..................................................238
Figure 8.5 Operation in Idle Mode........................................................................................239
Figure 8.6 Example of Idle Mode Setting Procedure ............................................................240
Figure 8.7 Operation in Repeat mode....................................................................................242
Figure 8.8 Example of Repeat Mode Setting Procedure .......................................................243
Figure 8.9 Data Bus in Single Address Mode .......................................................................244
Figure 8.10 Operation in Single Address Mode (when Sequential Mode Is Specified)..........246
Figure 8.11 Example of Single Address Mode Setting Procedure
(when Sequential Mode Is Specified) ..................................................................247
Figure 8.12 Operation in Normal Mode..................................................................................249
Figure 8.13 Example of Normal Mode Setting Procedure ......................................................250
Figure 8.14 Operation in Block Transfer Mode (BLKDIR = 0)..............................................252