Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 367 of 982
REJ09B0054-0600
11.3.1 Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU of the H8S/2227 Group
has a total of three TCR registers, one each for channels 0 to 2. In other groups, the TPU has a
total of six TCR registers, one each for channels 0 to 5. TCR register settings should be made only
when TCNT operation is stopped.
Bit Bit Name Initial Value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
These bits select the TCNT counter clearing source.
See tables 11.3 and 11.4 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2
rising edge). If phase counting mode is used on
channels 1, 2, 4
*
, and 5
*
, this setting is ignored and
the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
φ/4 or slower. When the input clock is φ/1 or when
overflow/underflow of another channel is selected,
this setting is ignored and the input clock is counted
at the falling edge of φ.
00: Count at rising edge
01: Count at falling edge
1×: Count at both edges
Legend: ×: Don’t care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables 11.5 to 11.10 for details.
Note: * Not available in the H8S/2227 Group.