Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 363 of 982
REJ09B0054-0600
Control logic
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TGRC
Channel 1
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Channel 0
TMDR
TSR
TCR
TIORH
TIER
Control logic for channels 0 to 2
TGRA
TCNT
TGRB
TGRD
TSYRTSTR
Clock input
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
Internal data bus
A/D conversion start request signal
TIORL
Module data bus
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
Internal clock:
External clock:
Channel 0:
Channel 1:
Channel 2:
Legend:
TSTR: Timer start register
TSYR: Timer synchronous register
TCR: Timer control register
TMDR: Timer mode register
TIOR (H, L): Timer I/O control registers (H, L)
TIER: Timer interrupt enable register
TSR: Timer status register
TGR (A, B, C, D) : Timer general registers (A, B, C, D)
Channel 2 Common
Bus interface
Figure 11.2 Block Diagram of TPU (H8S/2227 Group)