Datasheet

Section 10 I/O Ports
Rev. 6.00 Mar. 18, 2010 Page 353 of 982
REJ09B0054-0600
• PF3/LWR/ADTRG/IRQ3
The pin functions are switched as shown below according to the combination of operating
mode and the PF3DDR bit.
Operating mode Modes 4 to 6 Mode 7
Bus mode 16-bit bus
mode
8-bit bus mode ⎯
PF3DDR ⎯ 0 1 0 1
PF3 input pin PF3 output
pin
PF3 input pin PF3 output
pin
Pin functions LWR output
pin
ADTRG input pin
*
1
IRQ3 input pin
*
2
Notes: 1. When TRGS0 and TRGS1 are set to 1, this pin is ADTRG input.
2. When this pin is used as an external interrupt pin, do not specify other functions.
• PF2/WAIT
The pin functions are switched as shown below according to the combination of operating
mode, the WAITE bit, and the PF2DDR bit.
Operating mode Modes 4 to 6 Mode 7
WAITE 0 1 ⎯
PF2DDR 0 1 ⎯ 0 1
Pin functions PF2 input pin PF2 output
pin
WAIT input
pin
PF2 input pin PF2 output
pin
• PF1/BACK/BUZZ
The pin functions are switched as shown below according to the combination of operating
mode, the BUZZ bit in PFCR, and the PF1DDR bit.
Operating
mode
Modes 4 to 6 Mode 7
BRLE 0 1 ⎯
BUZZE 0 1 ⎯ 0 1
PF1DDR 0 1 ⎯ ⎯ 0 1 ⎯
Pin
functions
PF1
input pin
PF1
output
pin
BUZZ
output
pin
BACK
output
pin
PF1
input pin
PF1
output
pin
BUZZ
output pin