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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (12x12) 16-Bit 13 MHz I/O number 72
371372373374375376377378379380
Section 10 I/O Ports
Rev. 6.00 Mar. 18, 2010 Page 313 of 982
REJ09B0054-0600
• P13/TIOCD0/TCLKB/A23
The pin functions are switched as shown below according to the combination of operating
mode, the TPU channel 0 setting, TPSC2 to TPSC0 bits in TCR_0 to TCR_2, AE3 to AE0 bits
in PFCR and the P13DDR bit.
Operating mode Modes 4 to 6 Mode 7
AE3 to AE0 B'1111 Other than B'1111 ⎯
TPU Channel 0
Setting
*
1
⎯ Output Input or Initial Value Output Input or Initial Value
P13DDR ⎯ ⎯ 0 1 ⎯ 0 1
P13 input
pin
P13
output pin
P13 input
pin
P13
output pin
Pin functions A23
output
pin
TIOCD0
output
pin
TIOCD0 input
*
2
TIOCD0
output
pin
TIOCD0 input pin
*
2
TCLKB input pin
*
3
TCLKB input pin
*
3
Notes: 1. For the setting of the TPU channel, see section 11, 16-Bit Timer Pulse Unit (TPU).
2. This pin functions as TIOCD0 input when TPU channel 0 timer operating mode is set to
normal operating and IOD3 to IOD0 in TIORL_0 are set to 10xx.
3. This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2
are set to 101 or when channels 1 and 5 are set to phase counting mode.
• P12/TIOCC0/TCLKA/A22
The pin functions are switched as shown below according to the combination of operating
mode, the TPU channel 0 setting, TPSC2 to TPSC0 bits in TCR_0 to TCR_5, AE3 to AE0 bits
in PFCR, and the P12DDR bit.
Operating mode Modes 4 to 6 Mode 7
AE3 to AE0 B'1111 Other than B'1111 ⎯
TPU Channel 0
Setting
*
1
⎯ Output Input or Initial Value Output Input or Initial Value
P12DDR ⎯ ⎯ 0 1 ⎯ 0 1
P12 input
pin
P12
output pin
P12 input
pin
P12
output pin
Pin functions A22
output
pin
TIOCC0
output
pin
TIOCC0 input pin
*
2
TIOCC0
output
pin
TIOCC0 input pin
*
2
TCLKA input pin
*
3
TCLKA input pin
*
3
Notes: 1. For the setting of the TPU channel, see section 11, 16-Bit Timer Pulse Unit (TPU).
2. This pin functions as TIOCC0 input when TPU channel 0 timer operating mode is set to
normal operating and IOC3 to IOC0 in TIORL_0 are set to 10xx.
3. This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0 to TCR_5
are set to 100 or when channels 1 and 5 are set to phase counting mode.