Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 300 of 982
REJ09B0054-0600
9.5.7 Number of DTC Execution States
Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of
states required for each execution status.
Table 9.6 DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal 1 6 1 1 3
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 9.7 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
Internal I/O
Registers External Devices
Bus width 32 16 8 16 8 8 16 16
Access states 1 1 2 2 2 3 2 3
Vector read S
I
⎯ 1 ⎯ ⎯ 4 6 + 2 m 2 3 + m Execution
Status
Register information
read/write S
J
1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Byte data read S
K
1 1 2 2 2 3 + m 2 3 + m
Word data read S
K
1 1 4 2 4 6 + 2 m 2 3 + m
Byte data write S
L
1 1 2 2 2 3 + m 2 3 + m
Word data write S
L
1 1 4 2 4 6 + 2 m 2 3 + m
Internal operation S
M
1
Legend:
m: The number of wait states for accessing external devices.
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M