Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 296 of 982
REJ09B0054-0600
Table 9.5 lists the register information in block transfer mode. Figure 9.8 shows the memory
mapping in block transfer mode.
Table 9.5 Register Information in Block Transfer Mode
Name Abbreviation Function
DTC source address register SAR Designates source address
DTC destination address register DAR Designates destination address
DTC transfer count register AH CRAH Holds block size
DTC transfer count register AL CRAL Designates block size count
DTC transfer count register B CRB Transfer count
First block
Transfer
Block area
Nth block
DAR
or
SAR
SAR
or
DAR
·
·
·
Figure 9.8 Memory Mapping in Block Transfer Mode