Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 289 of 982
REJ09B0054-0600
CPU
DTC
DTCER
Source flag cleared
On-chip
peripheral
module
IRQ interrupt
Interrupt
request
Clear
Clear
controller
Clear request
Interrupt controller
Selection circuit
Interrupt mask
Select
DTVECR
Figure 9.2 Block Diagram of DTC Activation Source Control
9.4 Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
Register information should be located at an address that is a multiple of four within the range.
Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information.
In the case of chain transfer, register information should be located in consecutive areas as shown
in figure 9.3, and the register information start address should be located at the vector address
corresponding to the interrupt source. Figure 9.4 shows the correspondence between DTC vector
address and register information. The DTC reads the start address of the register information from
the vector address set for each activation source, and then reads the register information from that
start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Note: * Normal mode cannot be used in this LSI.