Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 286 of 982
REJ09B0054-0600
9.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI)
DTCER is a set of registers to specify the DTC activation interrupt source, and comprised of eight
registers; DTCERA to DTCERG, and DTCERI. The correspondence between interrupt sources
and DTCE bits, and vector numbers generated by the interrupt controller are shown in table 9.2.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. When multiple activation sources are to be set at one time, only at the initial setting,
writing data is enabled after executing a dummy read on the relevant register with all the interrupts
being masked.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
DTCEn7
DTCEn6
DTCEn5
DTCEn4
DTCEn3
DTCEn2
DTCEn1
DTCEn0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable
0: Disables an interrupt for DTC activation.
1: Specifies a relevant interrupt source as a DTC
activation source.
[Clearing conditions]
• When the DISEL bit in MRB is 1 and the data
transfer has ended
• When the specified number of transfers have
ended
[Retaining condition]
When the DISEL bit is 0 and the specified number
of transfers have not been completed
Note: n = A to G, and I