Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 284 of 982
REJ09B0054-0600
Bit Bit Name Initial Value R/W Description
0 Sz Undefined ⎯ DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend: ×: Don’t care
9.2.2 DTC Mode Register B (MRB)
MRB is an 8-bit register that selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 CHNE Undefined ⎯ DTC Chain Transfer Enable
This bit specifies a chain transfer. For details, refer
to section 9.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of
DTCER, are not performed.
0: DTC data transfer completed (waiting for start)
1: DTC chain transfer (reads new register
information and transfers data)
6 DISEL Undefined ⎯ DTC Interrupt Select
This bit specifies whether CPU interrupt is disabled
or enabled after a data transfer.
0: Interrupt request is issued to the CPU when the
specified data transfer is completed
1: DTC issues interrupt request to the CPU in every
data transfer (DTC does not clear the interrupt
request flag that is a cause of the activation)
5 to
0
⎯ Undefined ⎯ Reserved
These bits have no effect on DTC operation. The
write value should always be 0.