Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 283 of 982
REJ09B0054-0600
• DTC enable registers A to G, and I (DTCERA to DTCERG, and DTCERI)
• DTC vector register (DTVECR)
9.2.1 DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7
6
SM1
SM0
Undefined
Undefined
⎯
⎯
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0×: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
5
4
DM1
DM0
Undefined
Undefined
⎯
⎯
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0×: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
3
2
MD1
MD0
Undefined
Undefined
⎯
⎯
DTC Mode 1 and 0
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1 DTS Undefined ⎯ DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in
repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area