Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 254 of 982
REJ09B0054-0600
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at
this point, an interrupt request is sent to the CPU or DTC.
Figure 8.16 shows the operation flow in block transfer mode.
Acquire bus
ETCRAL = ETCRAL 1
Transfer request?
ETCRAL = H'00
Release bus
BLKDIR = 0
ETCRAL = ETCRAH
ETCRB = ETCRB 1
ETCRB = H'0000
Start
(DTE = DTME = 1)
Read address specified by MARA
MARA = MARA + SAIDE ( 1)
SAID
2
DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE ( 1)
DAID
2
DTSZ
MARB = MARB DAIDE ( 1)
DAID
2
DTSZ
ETCRAH
MARA = MARA
SAIDE ( 1)
SAID
2
DTSZ
ETCRAH
No
Yes
No
Yes
No
Yes
No
Yes
Clear DTE bit to 0
to end transfer
Figure 8.16 Operation Flow in Block Transfer Mode