Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 249 of 982
REJ09B0054-0600
Figure 8.12 illustrates operation in normal mode.
Address T
A
Address B
A
Transfer
Address T
B
Legend:
Address
Address
Address
Address
Where :
Address B
B
= L
A
= L
B
= L
A
+ SAIDE ( 1)
SAID
(2
DTSZ
(N 1))
= L
B
+ DAIDE ( 1)
DAID
(2
DTSZ
(N 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
T
A
T
B
B
A
B
B
L
A
L
B
N
Figure 8.12 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests. With auto-request,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends.