Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 231 of 982
REJ09B0054-0600
8.3.7 DMA Terminal Control Register (DMATCR)
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Bit Bit Name Initial Value R/W Description
7, 6 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
5 TEE1 0 R/W Transfer End Enable 1
Enables or disables transfer end pin 1 (TEND1)
output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
4 TEE0 0 R/W Transfer End Enable 0
Enables or disables transfer end pin 0 (TEND0)
output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
3 to 0 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
8.4 Activation Sources
DMAC activation sources consist of internal interrupt requests, external requests, and auto-
requests. The DMAC activation sources that can be specified depend on the transfer mode and
channel, as shown in table 8.3.