Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 226 of 982
REJ09B0054-0600
Bit Bit Name Initial Value R/W Description
5 DTME0 0 R/W Data Transfer Master Enable 0
Together with the DTE0 bit, this bit controls
enabling or disabling of data transfer on
channel 0. When both the DTME0 bit and DTE0
bit are set to 1, transfer is enabled for channel
0.
If channel 0 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME0 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When
the DTME0 bit is subsequently set to 1 again,
the interrupted transfer is resumed. In block
transfer mode, however, the DTME0 bit is not
cleared by an NMI interrupt, and transfer is not
interrupted.
0: Data transfer is disabled
1: Data transfer is enabled
[Clearing conditions]
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME0 bit
[Setting condition]
When 1 is written to DTME0 after reading
DTME0 = 0