Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 221 of 982
REJ09B0054-0600
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer End Interrupt Enable 1B
Data Transfer End Interrupt Enable 1A
Data Transfer End Interrupt Enable 0B
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit
is set to 1 when DTE = 0, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE bit to 1.
0: Transfer end interrupt is disabled
1: Transfer end interrupt is enabled
(2) Full Address Mode
• DMABCRH
Bit Bit Name Initial Value R/W Description
15 FAE1 0 R/W Full Address Enable 1
Specifies whether channel 1 is to be used in
short address mode or full address mode.
In full address mode, channels 1A and 1B are
used together as channel 1.
0: Short address mode
1: Full address mode
14 FAE0 0 R/W Full Address Enable 0
Specifies whether channel 0 is to be used in
short address mode or full address mode.
In full address mode, channels 0A and 0B are
used together as channel 0.
0: Short address mode
1: Full address mode