Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 215 of 982
REJ09B0054-0600
• DMACR_0B and DMACR_1B
Bit Bit Name Initial Value R/W Description
7 ⎯ 0 R/W Reserved
This bit can be read from or written to.
However, the write value should always be 0.
6
5
DAID
DAIDE
0
0
R/W
R/W
Destination Address Increment/Decrement
Destination Address Increment/Decrement
Enable
These bits specify whether destination address
register MARB is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by
1
• When DTSZ = 1, MARB is incremented by
2
10: MARB is fixed
11: MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by
1
• When DTSZ = 1, MARB is decremented by
2
4 — 0 R/W Reserved
This bit can be read from or written to.
However, the write value should always be 0.