Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 213 of 982
REJ09B0054-0600
(2) Full Address Mode
• DMACR_0A and DMACR_1A
Bit Bit Name Initial Value R/W Description
15 DTSZ 0 R/W Data Transfer Size
Selects the size of data to be transferred at
one time.
0: Byte-size transfer
1: Word-size transfer
14
13
SAID
SAIDE
0
0
R/W
R/W
Source Address Increment/Decrement
Source Address Increment/Decrement Enable
These bits specify whether source address
register MARA is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARA is fixed
01: MARA is incremented after a data transfer
• When DTSZ = 0, MARA is incremented by
1
• When DTSZ = 1, MARA is incremented by
2
10: MARA is fixed
11: MARA is decremented after a data transfer
• When DTSZ = 0, MARA is decremented by
1
• When DTSZ = 1, MARA is decremented by
2