Datasheet

Rev. 6.00 Mar. 18, 2010 Page xxv of lx
REJ09B0054-0600
7.10.1 Operation .............................................................................................................199
7.10.2 Bus Transfer Timing............................................................................................200
7.10.3 External Bus Release Usage Note........................................................................200
7.11 Resets and the Bus Controller...........................................................................................201
Section 8 DMA Controller (DMAC) ................................................................ 203
8.1 Features.............................................................................................................................203
8.2 Input/Output Pins..............................................................................................................205
8.3 Register Descriptions........................................................................................................205
8.3.1 Memory Address Registers (MARA and MARB)...............................................207
8.3.2 I/O Address Registers (IOARA and IOARB)......................................................207
8.3.3 Execute Transfer Count Registers (ETCRA and ETCRB)...................................208
8.3.4 DMA Control Registers (DMACRA and DMACRB) .........................................209
8.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............218
8.3.6 DMA Write Enable Register (DMAWER) ..........................................................229
8.3.7 DMA Terminal Control Register (DMATCR).....................................................231
8.4 Activation Sources............................................................................................................231
8.4.1 Activation by Internal Interrupt Request..............................................................232
8.4.2 Activation by External Request ...........................................................................233
8.4.3 Activation by Auto-Request.................................................................................233
8.5 Operation...........................................................................................................................234
8.5.1 Transfer Modes....................................................................................................234
8.5.2 Sequential Mode ..................................................................................................236
8.5.3 Idle Mode.............................................................................................................239
8.5.4 Repeat Mode........................................................................................................241
8.5.5 Single Address Mode...........................................................................................244
8.5.6 Normal Mode.......................................................................................................248
8.5.7 Block Transfer Mode...........................................................................................251
8.5.8 Basic Bus Cycles..................................................................................................256
8.5.9 DMA Transfer (Dual Address Mode) Bus Cycles...............................................257
8.5.10 DMA Transfer (Single Address Mode) Bus Cycles.............................................265
8.5.11 Multi-Channel Operation.....................................................................................271
8.5.12 Relation between DMAC and External Bus Requests, and DTC ........................272
8.5.13 DMAC and NMI Interrupts..................................................................................272
8.5.14 Forced Termination of DMAC Operation............................................................273
8.5.15 Clearing Full Address Mode................................................................................274
8.6 Interrupt Sources...............................................................................................................275
8.7 Usage Notes ......................................................................................................................276
8.7.1 DMAC Register Access during Operation...........................................................276
8.7.2 Module Stop.........................................................................................................277