Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 201 of 982
REJ09B0054-0600
7.11 Resets and the Bus Controller
In a power-on reset, this LSI, including the bus controller, enters the reset state at that point, and
an executing bus cycle is discontinued.
In a manual reset, the bus controller's registers and internal state are maintained, and an executing
external bus cycle is completed. In this case, WAIT input is ignored and write data is not
guaranteed.
When the DMAC* is initialized at the manual reset, DACK and TEND output is disabled. The
DMAC* operates as I/O port controlled by DDR and DR.
Note: * Supported only by the H8S/2239 Group.