Datasheet

Rev. 6.00 Mar. 18, 2010 Page xxiv of lx
REJ09B0054-0600
6.4.3 CMFA and CMFB ...............................................................................................163
6.4.4 PC Break Interrupt when DTC and DMAC Is Bus Master..................................163
6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, and RTS Instruction.....................................................................163
6.4.6 I Bit Set by LDC, ANDC, ORC, and XORC Instruction.....................................164
6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction..........164
6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction............................................................................................................164
Section 7 Bus Controller....................................................................................165
7.1 Features.............................................................................................................................165
7.2 Input/Output Pins..............................................................................................................167
7.3 Register Descriptions........................................................................................................167
7.3.1 Bus Width Control Register (ABWCR)...............................................................168
7.3.2 Access State Control Register (ASTCR) .............................................................168
7.3.3 Wait Control Registers H and L (WCRH, WCRL)..............................................169
7.3.4 Bus Control Register H (BCRH) .........................................................................172
7.3.5 Bus Control Register L (BCRL) ..........................................................................173
7.3.6 Pin Function Control Register (PFCR) ................................................................174
7.4 Bus Control.......................................................................................................................175
7.4.1 Area Divisions .....................................................................................................175
7.4.2 Bus Specifications................................................................................................176
7.4.3 Bus Interface for Each Area.................................................................................177
7.4.4 Chip Select Signals ..............................................................................................178
7.5 Basic Timing.....................................................................................................................178
7.5.1 On-Chip Memory (ROM, RAM) Access Timing................................................179
7.5.2 On-Chip Peripheral Module Access Timing........................................................180
7.5.3 External Address Space Access Timing ..............................................................181
7.6 Basic Bus Interface ...........................................................................................................181
7.6.1 Data Size and Data Alignment.............................................................................181
7.6.2 Valid Strobes........................................................................................................182
7.6.3 Basic Timing........................................................................................................183
7.6.4 Wait Control ........................................................................................................190
7.7 Burst ROM Interface.........................................................................................................192
7.7.1 Basic Timing........................................................................................................192
7.7.2 Wait Control ........................................................................................................194
7.8 Idle Cycle..........................................................................................................................194
7.9 Bus Release.......................................................................................................................197
7.9.1 Bus Release Usage Note ......................................................................................198
7.10 Bus Arbitration..................................................................................................................199