Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 196 of 982
REJ09B0054-0600
T
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Address bus
φφ
Bus cycle A Bus cycle B
(a) Idle cycle not inserted
(ICIS1 = 0)
Possibility of overlap between
CS (area B) and RD
Address bus
Bus cycle A Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
CS (area A)
CS (area B)
RD RD
CS (area A)
CS (area B)
Figure 7.23 Relationship between Chip Select (CS) and Read (RD)
Table 7.4 shows pin states in an idle cycle.
Table 7.4 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of next bus cycle
D15 to D0 High impedance
CSn High
AS High
RD High
HWR High
LWR High