Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 194 of 982
REJ09B0054-0600
7.7.2 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.6.4, Wait
Control.
Wait states cannot be inserted in a burst cycle.
7.8 Idle Cycle
When this LSI accesses external space, it can insert a 1-state idle cycle (T
I
) between bus cycles in
the following two cases: (1) when read accesses between different areas occur consecutively, and
(2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, with a long output floating time, and
high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an
idle cycle is inserted at the start of the second read cycle.
Figure 7.21 shows an example of the operation in this case. In this example, bus cycle A is a
read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from
SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a
collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an
idle cycle is inserted, and a data collision is prevented.
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output floating time
Data collision
(a) Idle cycle not inserted
(ICIS1 = 0)
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
I
T
1
Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
T
2
CS (area A)
CS (area B)
CS (area A)
CS (area B)
Figure 7.21 Example of Idle Cycle Operation (1)