Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 190 of 982
REJ09B0054-0600
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Valid
Write
Note: n = 7 to 0
T
3
Figure 7.17 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
7.6.4 Wait Control
When accessing external space, this LSI can extend the bus cycle by inserting one or more wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
(1) Program Wait Insertion
From 0 to 3 wait states can be inserted automatically between the T
2
state and T
3
state on an
individual area basis in 3-state access space, according to the settings of WCRH and WCRL.