Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 185 of 982
REJ09B0054-0600
16-Bit 2-State Access Space: Figures 7.12 to 7.14 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Write
High
Note: n = 7 to 0
High impedance
Figure 7.12 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)