Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 183 of 982
REJ09B0054-0600
7.6.3 Basic Timing
8-Bit 2-State Access Space: Figure 7.10 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
(16-bit bus
mode)
D15 to D8
Valid
D7 to D0
High impedance
High impedance
Write
High
Note: n = 7 to 0
LWR
(8-bit bus
mode)
Figure 7.10 Bus Timing for 8-Bit 2-State Access Space