Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 180 of 982
REJ09B0054-0600
7.5.2 On-Chip Peripheral Module Access Timing
The on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 7.6 shows the access
timing for the on-chip peripheral modules. Figure 7.7 shows the pin states.
T
1
T
2
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 7.6 On-Chip Peripheral Module Access Cycle
T
1
T
2
Bus cycle
Unchanged
Address bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 7.7 Pin States during On-Chip Peripheral Module Access