Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 178 of 982
REJ09B0054-0600
Only the basic bus interface can be used for the area 7.
7.4.4 Chip Select Signals
This LSI can output chip select signals (CS7 to CS0) to areas 7 to 0, the signal being driven low
when the corresponding external space area is accessed. Figure 7.3 shows an example of CSn (n =
7 to 0) output timing. Enabling or disabling of the CSn signal is performed by setting the data
direction register (DDR) for the port corresponding to the particular CSn pin.
In ROM-disabled extended mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS7 to CS1 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS7 to CS1.
In ROM-enabled extended mode, pins CS7 to CS0 are all placed in the input state after a power-on
reset, and so the corresponding DDR should be set to 1 when outputting signals CS7 to CS0. For
details, see section 10, I/O Ports.
Bus cycle
T
1
T
2
T
3
Area n external address
Address bus
φ
CSn
Figure 7.3 CSn Signal Output Timing (n = 0 to 7)
7.5 Basic Timing
The CPU is driven by a system clock (φ), denoted by the symbol φ. The period from one rising
edge of φ to the next is referred to as a “state”. The memory cycle or bus cycle consists of one,
two, or three states. Different methods are used to access on-chip memory, on-chip peripheral
modules, and the external address space.