Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 174 of 982
REJ09B0054-0600
7.3.6 Pin Function Control Register (PFCR)
Bit Bit Name Initial Value R/W Description
7, 6 ⎯ All 0 R/W Reserved
The write value should always be 0.
5 BUZZE 0 R/W BUZZ Output Enable:
This bit selects enabling or disabling of BUZZ output
from pin PF1. WDT_1 input clock that is selected by
PSS, and CKS2 to CKS0 bits is output as BUZZ signal.
0: PF1 input/output pin
1: BUZZ output pin
4 ⎯ 0 R/W Reserved
The write value should always be 0.
3
2
1
0
AE3
AE2
AE1
AE0
1/0*
1/0*
0
1/0*
R/W
R/W
R/W
R/W
Address Output Enable 3 to 0
These bits select enabling or disabling of address
outputs A23 to A8 in ROMless extended mode and
modes with ROM.
When a pin is enabled for address output, the address is
output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an
output port when the corresponding DDR bit is set to 1.
0000: A23 to A8 output disabled
0001: A8 output enabled; A23 to A9 output disabled
0010: A9, A8 output enabled; A23 to A10 output disabled
0011: A10 to A8 output enabled; A23 to A11 output disabled
0100: A11 to A8 output enabled; A23 to A12 output disabled
0101: A12 to A8 output enabled; A23 to A13 output disabled
0110: A13 to A8 output enabled; A23 to A14 output disabled
0111: A14 to A8 output enabled; A23 to A15 output disabled
1000: A15 to A8 output enabled; A23 to A16 output disabled
1001: A16 to A8 output enabled; A23 to A17 output disabled
1010: A17 to A8 output enabled; A23 to A18 output disabled
1011: A18 to A8 output enabled; A23 to A19 output disabled
1100: A19 to A8 output enabled; A23 to A20 output disabled
1101: A20 to A8 output enabled; A23 to A21 output disabled
1110: A21 to A8 output enabled; A23, A22 output disabled
1111: A23 to A8 output enabled
Note: * In modes 4 and 5, initial value of each bit is 1. In modes 6 and 7, initial value of each bit
is 0.