Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 173 of 982
REJ09B0054-0600
7.3.5 Bus Control Register L (BCRL)
BCRL performs selection of the external bus-released state protocol, and enabling or disabling of
WAIT pin input.
Bit Bit Name Initial Value R/W Description
7 BRLE 0 R/W Bus release enable
Enables or disables external bus release.
0: External bus release is disabled. BREQ and BACK
can be used as I/O ports
1: External bus release is enabled
6 — 0 R/W Reserved
The write value should always be 0.
5 — 0 — Reserved
This bit is always read as 0 and cannot be modified.
4 — 0 R/W Reserved
The write value should always be 0.
3 — 1 R/W Reserved
The write value should always be 1.
2, 1 — All 0 R/W Reserved
The write value should always be 0.
0 WAITE 0 R/W WAIT pin enable
Selects enabling or disabling of wait input by the WAIT
pin.
0: Wait input by WAIT pin disabled. WAIT pin can be
used as I/O port
1: Wait input by WAIT pin enabled