Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 172 of 982
REJ09B0054-0600
7.3.4 Bus Control Register H (BCRH)
BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0.
Bit Bit Name Initial Value R/W Description
7 ICIS1 1 R/W Idle Cycle Insert 1
Selects whether or not one idle cycle state is to be
inserted between bus cycles when successive external
read cycles are performed in different areas.
0: Idle cycle not inserted in case of successive external
read cycles in different areas
1: Idle cycle inserted in case of successive external read
cycles in different areas
6 ICIS0 1 R/W Idle Cycle Insert 0
Selects whether or not one idle cycle state is to be
inserted between bus cycles when successive external
read and write cycles are performed.
0: Idle cycle not inserted in case of successive external
read and write cycles
1: Idle cycle inserted in case of successive external read
and write cycles
5 BRSTRM 0 R/W Burst ROM enable
Selects whether area 0 is used as a burst ROM
interface.
0: Area 0 is basic bus interface
1: Area 0 is burst ROM interface
4 BRSTS1 1 R/W Burst Cycle Select 1
Selects the number of burst cycles for the burst ROM
interface.
0: Burst cycle comprises 1 state
1: Burst cycle comprises 2 states
3 BRSTS0 0 R/W Burst Cycle Select 0
Selects the number of words that can be accessed in a
burst ROM interface burst access.
0: Max. 4 words in burst access
1: Max. 8 words in burst access
2 to
0
— All 0 R/W Reserved
The write value should always be 0.