Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 165 of 982
REJ09B0054-0600
Section 7 Bus Controller
This LSI has a built-in bus controller (BSC) that manages the external address space divided into
eight areas. The bus controller also has a bus arbitration function, and controls the operation of the
internal bus masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC).
Note: * Supported only by the H8S/2239 Group.
7.1 Features
• Manages external address space in area units
⎯ Manages the external space as 8 areas of 2-Mbytes
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interface can be set
• Basic bus interface
⎯ Chip select (CS7 to CS0) can be output for areas 7 to 0
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
• Burst ROM interface
⎯ Burst ROM interface can be selected for area 0
⎯ One or two states can be selected for the burst cycle
• Idle cycle insertion
⎯ Idle cycle can be inserted between consecutive read accesses to different areas
⎯ Idle cycle can be inserted before a write access to an external area immediately after a read
access to an external area
• Bus arbitration
⎯ The on-chip bus arbiter arbitrates bus mastership among CPU, DMAC*, and DTC.
• Other features
⎯ External bus release function
Note: * Supported only by the H8S/2239 Group.