Datasheet

Section 6 PC Break Controller (PBC)
Rev. 6.00 Mar. 18, 2010 Page 162 of 982
REJ09B0054-0600
• When the SLEEP instruction causes a transition to software standby mode or watch mode:
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(D).
SLEEP instruction
execution
High-speed
(medium-speed)
mode
SLEEP instruction
execution
Subactive
mode
System clock
→ subclock
Direct transition
exception handling
PC break exception
handling
Execution of instruction
after sleep instruction
Subclock →
system clock,
oscillation settling time
SLEEP instruction
execution
Transition to
respective mode
Direct transition
exception handling
PC break exception
handling
Execution of instruction
after sleep instruction
PC break exception
handling
Execution of instruction
after sleep instruction
(A)
(B) (C)
(D)
SLEEP instruction
execution
Figure 6.2 Operation in Power-Down Mode Transitions
6.3.5 When Instruction Execution Is Delayed by One State
While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
ROM or RAM.
• When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be
one state later than in normal operation.
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,