Datasheet

Section 5 Interrupt Controller
Rev. 6.00 Mar. 18, 2010 Page 156 of 982
REJ09B0054-0600
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5.6.5 IRQ Interrupt
When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In
software standby mode, watch mode, subactive mode and subsleep mode, the input is accepted
asynchronously. For details on the input conditions, see Operating Timing in section 27, Electrical
Characteristics.
5.6.6 NMI Interrupts Usage Notes
The NMI interrupt is part of the exception processing performed cooperatively by the LSI’s
internal interrupt controller and the CPU when the system is operating normally under the
specified electrical conditions. No operations, including NMI interrupts, are guaranteed when
operation is not normal (runaway status) due to software problems or abnormal input to the LSI’s
pins. In such cases, the LSI may be restored to the normal program execution state by applying an
external reset.