Datasheet

Section 5 Interrupt Controller
Rev. 6.00 Mar. 18, 2010 Page 140 of 982
REJ09B0054-0600
Vector
Address*
1
Interrupt Source
Origin of
Interrupt Source
Vector
Number
Advanced
Mode IPR*
2
Priority
DMAC
*
5
DEND0A (completion of
channel 0/channel 0A transfer)
72 H'0120 IPRJ6 to IPRJ4 High
DEND0B (completion of
channel 0B transfer)
73 H'0124
DEND1A (completion of
channel 1/channel 1A transfer)
74 H'0128
DEND1B (completion of
channel 1B transfer)
75 H'012C
ERI0 (receive error 0) 80 H'0140 IPRJ2 to IPRJ0
RXI0 (receive completion 0) 81 H'0144
TXI0 (transmit data empty 0) 82 H'0148
SCI
channel 0
TEI0 (transmit end 0) 83 H'014C
ERI1 (receive error 1) 84 H'0150 IPRK6 to IPRK4 SCI
channel 1
RXI1 (receive completion 1) 85 H'0154
TXI1 (transmit data empty 1) 86 H'0158
TEI1 (transmit end 1) 87 H'015C
SCI
channel 2
*
3
ERI2 (receive error 2) 88 H'0160 IPRK2 to IPRK0
RXI2 (receive completion 2) 89 H'0164
TXI2 (transmit data empty 2) 90 H'0168
TEI2 (transmit end 2) 91 H'016C
8-bit timer channel 2
*
4
CMIA2 (compare-match A2) 92 H'0170 IPRL6 to IPRL4
CMIB2 (compare-match B2) 93 H'0174
OVI2 (overflow 2) 94 H'0178
⎯ Reserved 95 H'017C Low